A programmable logic device (PLD) includes memory circuitry that can be used as random access memory (RAM). More particularly, the PLD includes a plurality of look-up tables (LUTs) that are not needed for normal LUT-based logic and such LUTs are used to provide the above-mentioned user-accessible RAM. Such RAM is “distributed RAM” because, rather than being in a block of dedicated user RAM circuitry, it is distributed over the LUTs on the PLD.
A write address register stores write addresses of a location of a memory cell of the RAM. It is difficult to configure the write address register in such a manner to be able to quickly and consistently write data to the memory cell, especially when data is read from the memory cell during the same clock cycle in which the write is performed.